This invention relates to a data synchronizer as might be used in reading data from a computer disk drive, or in receiving data over a serial data communications link.
As an example, FIG. 1 illustrates the process of reading data from a computer disk drive. Flux reversals 10 on the rotating magnetic disk 12 are sensed by a read head 14 and amplified by read/write amplifier 16. The analog signal 18 is then passed through a pulse peak detector 20 to generate a stream of digital input data 22 in which the rising edge of a pulse represents a flux reversal 10.
The time positions of pulses in the input data 22 can vary or "jitter" due to difficulty in precisely replicating the time positions of flux reversals 10 on the disk 12. A data synchronizer 24 functions to synchronize the input data 22 into output data 26 of evenly timed "windows" in which a pulse is present or absent.
Completing FIG. 1, a decoder 28 converts the output data 26 into synchronous clock signals 30 and NRZ-encoded data signals 32 for processing by a disk data controller 34 and eventual use by a computer system 36.
Another example is the receiving of data over a serial data communications link. The time position of pulses in the received data can vary or "jitter" due to frequency-dependent variations in the communications channel, or due to difficulty in precisely detecting the time positions of transitions in the received signal. Again, a data synchronizer can be used to synchronize the received data into output data of evenly timed windows in which data appears.
FIG. 2 shows a known approach to performing the synchronization function of the data synchronizer 24. A voltage controlled oscillator (VCO) signal 38 is produced at the mean data rate of the input data 22. The frequency of the VCO signal 38 and its phase, the time position of its rising or falling edges, are locked in position relative to the long term average position of pulses in the input data 22 by a phase lock loop (PLL) which compares the input data 22 and the VCO signal 38 and adjusts the frequency of the VCO signal 38 to correct any deviation.
It is common to lock a rising edge of the VCO signal 38 to the center of the pulse positions of the input data 22. This can be done by locking the VCO signal 38 to the input data 22 delayed for a time period of one half the period of the VCO signal 38.
In this way, the VCO signal 38 defines a "window" 40 for receiving a pulse in the input data 22, with the rising edge of the VCO signal 38 defining a nominal window center 44, and the falling edge of the VCO signal 38 defining the end of one window and the start of the next window.
When there is a pulse in the input data 22 anywhere within a window 40, the rising edge of the VCO signal pulse can capture the pulse. This is commonly done by applying the input data 22 to the data input of an edge triggered flip-flop which is clocked or enabled by the VCO signal 38. If there is a data pulse in the input data 22, when the VCO signal 38 clocks the flip-flop, the flip-flop will change state. If there is no pulse in the input data 22, the flip-flop will not change state when clocked by the VCO signal 38.
In this way, the state of the flip-flop can be read to produce output data 26. Output data 26 corresponds to the input data 22, but is delayed by up to one window period, and has no jitter since it is synchronized to the VCO signal 38.
The time position of a pulse in the input data 22 can vary or "jitter" early or late within a window 40. An early pulse 42 has its rising edge ahead of the nominal window center 44. A late pulse 46 has its rising edge after the nominal window center 44. It is desirable to recognize pulses occurring anywhere within the window. To accomplish this, it is important that the nominal window center 44 occur exactly one-half way through the window 40. Any centering error reduces the ability to detect very early or very late pulses.
It is also desirable to have a "strobe" function in which the window 40 can be intentionally moved early or late with respect to the nominal window center 44. This strobe function can be used to compensate for windows 40 which were not accurately centered, or to recover data which consistently occurs shifted with respect to the nominal window center 44.
It is known to center the window by inserting a one-half VCO period delay in the input data 22 before locking the VCO signal 38 to it. The one-half period delay places the nominal window center 44 one-half way through the window 40. This delay line can be made in a combination of digital and analog form by use of a digital counter such as a chain of flip-flops or gates. Such a delay line is shown in "A 33 Mbit/sec Data Synchronizing Phase-Locked-Loop Circuit" by W. Llewellyn, M. Wong, G. Tietz, and P. Tucci as presented at the IEEE International Solid State Circuits Conference 1988. An advantage of this approach is that it is possible to "strobe" or vary the delay of the delay line by varying the current into the delay line and the circuit can operate over a wide range of data rates. Disadvantages of this approach are that it is difficult to achieve an absolute match to the center of the window since much circuitry is involved, and that large values of strobe reduce the pulse recognition performance of the data synchronizer, since the position of the delayed data is being adjusted rather than adjusting the position of the window 40 relative to the nominal window center 44.
Another known method of data synchronization is to use a VCO signal 38 and its complement or opposite phase, a -VCO signal. The VCO signal 38 is locked to the delayed input data, but the input data 22 is captured in a flip-flop clocked on the -VCO signal. In this method, window centering is controlled by the duty cycle between the VCO and -VCO signals. This duty cycle can be controlled, for example, by control of the current ratio into two legs of an emitter-coupled relaxation oscillator. In this method the window is well centered, but is difficult to strobe.